In reading out data stored in a semiconductor device, a voltage higher than the power supply voltage is necessary, in some cases. For example, on a flash memory that uses the power supply voltage of 3 V, a voltage of 5 V has to be applied at the time of reading the data. On this account, a booster circuit is necessary for boosting the power supply voltage to generate a gate voltage.
With respect to the flash memory, it takes approximately 100 nanoseconds to read out the data, and boosting has to be completed in 20 to 30 nanoseconds. This is why the booster circuit is mainly employed as a circuit for boosting in the flash memory. The booster circuit boosts the voltage up to a desired one rapidly with a control signal different from a clock signal.
Referring to FIG. 1 (Prior Art), a description will be given of a boost operation at the time of reading out the data. FIG. 1 (Prior Art) shows a voltage generating circuit 11 supplying the voltage and an X decoder 6 selectively supplying the voltage from the voltage generating circuit 11 to a word line (WL). Once the data starts to be read out, a switch 25 shown in FIG. 1 (Prior Art) turns on, and a power supply voltage Vcc (26) is coupled with a node A. This charges the node A connected to the selected word line (WL) and the X decoder 6, to the Vcc level, as shown in FIG. 2 (Prior Art).
A booster circuit 20 includes a pulse generating circuit 21 and a boosting capacitor 22, and the pulse generating circuit 21 is connected to the node A through the boosting capacitor 22. The node A is charged up to Vcc, the switch 25 is opened to disconnect the node A from the power supply voltage Vcc (26), and generates positive pulses are output from the pulse generating circuit 21 in the booster circuit 20. FIG. 2 (Prior Art) shows the voltage of a node B that connects the pulse generating circuit 21 and the boosting capacitor 22. A one-shot positive pulse output is applied to the boosting capacitor 22 from the pulse generating circuit 21, and the node A is boosted up to the level higher than Vcc by capacitive coupling of the boosting capacitor 22. This boosted voltage is applied to, for example, a gate of a memory cell that selects 5 V.
Japanese Patent Application Publication No. 2001-35174 discloses a semiconductor memory device having a booster circuit in which changes in the power supply voltage and those in temperature in the boosting voltage have been compensated.
While the pulse generating circuit 21 is generating the positive pulse outputs, the word line (WL) that has been boosted by the booster circuit 20 maintains the boosted level. However, in fact, a minute leakage current occurs in the X decoder 6, and accordingly, the voltage level of the node A gradually decreases as time goes, as shown in FIG. 2 (Prior Art).
If the data is just read out of one memory cell, it takes a short period of time and the decreased voltage does not cause a problem. However, if one word line (WL) has to be boosted up for a long time as a burst reading, the decreased voltage in the node A is a problem. Japanese Patent Application Publication No. 2001-35174 does not describe the aforementioned problem or means for solving the problem.